Rewriting environment for arithmetic circuit verification

DOI10.29007/RSWKzbMATH Open1415.68151OpenAlexW2908208232MaRDI QIDQ5222992FDOQ5222992

Authors: Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej Ciesielski 

Publication date: 4 July 2019

Published in: EPiC Series in Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.29007/rswk

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zbMATH Keywords

computer algebraarithmetic circuitsformal verification

Mathematics Subject Classification ID

Grammars and rewriting systems (68Q42) Specification and verification (program logics, model checking, etc.) (68Q60)

Cited In (7)

• Rewrite systems for integer arithmetic
• Automated and scalable verification of integer multipliers
• petBoss
• Reveal: A Formal Verification Tool for Verilog Designs
• Designing arithmetic circuits by refinement in Ruby
• Rewrite based hardware verification with ReDuX
• Incremental column-wise verification of arithmetic circuits using computer algebra

Uses Software

• SINGULAR
• STABLE
• ABC

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