Incremental column-wise verification of arithmetic circuits using computer algebra
DOI10.1007/S10703-018-00329-2zbMATH Open1506.68056DBLPjournals/fmsd/KaufmannBK20OpenAlexW2916007847WikidataQ104101648 ScholiaQ104101648MaRDI QIDQ2225473FDOQ2225473
Authors: Daniela Kaufmann, Armin Biere, M. Kauers 
Publication date: 8 February 2021
Published in: Formal Methods in System Design (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/s10703-018-00329-2
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Cites Work
- Graph-Based Algorithms for Boolean Function Manipulation
- Theory and Applications of Satisfiability Testing
- An algorithm for finding the basis elements of the residue class ring of a zero dimensional polynomial ideal
- Title not available (Why is that?)
- Simulating circuit-level simplifications on CNF
- Computer arithmetic algorithms.
- An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths
- Verification of arithmetic circuits using binary moment diagrams
Cited In (6)
- Polynomial formal verification of multipliers
- An Algebraic Approach for Proving Data Correctness in Arithmetic Data Paths
- Formal Verification of Integer Multiplier Circuits Using Algebraic Reasoning: A Survey
- Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry
- Practical algebraic calculus and Nullstellensatz with the checkers Pacheck and Pastèque and Nuss-Checker
- Rewriting environment for arithmetic circuit verification
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