Via Minimization with Pin Preassignments and Layer Preference
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Cites work
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(18)- Constrained via minimization for three-layer routing
- An integrated approach to routing and via minimization
- The pin redistribution problem in multi-chip modules
- Steiner tree packing revisited
- On the diameter of cut polytopes
- A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization
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- Solving VLSI design and DNA sequencing problems using bipartization of graphs
- Partitioning planar graphs: a fast combinatorial approach for max-cut
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- Optimal control of plotting and drilling machines: A case study
- From equipartition to uniform cut polytopes: extended polyhedral results
- A polynomial-time recursive algorithm for some unconstrained quadratic optimization problems
- Conjugate conflict continuation graphs for multi-layer constrained via minimization
- Mathematical methods for physical layout of printed circuit boards: an overview
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