Lightweight Implementations of SHA-3 Candidates on FPGAs (Q3104746): Difference between revisions
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| Property / full work available at URL: https://doi.org/10.1007/978-3-642-25578-6_20 / rank | |||
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| Property / cites work: Keccak / rank | |||
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| Property / cites work: A Low-Area Yet Performant FPGA Implementation of Shabal / rank | |||
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| Property / cites work: Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs / rank | |||
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| Property / cites work: Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs / rank | |||
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Latest revision as of 18:39, 4 July 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Lightweight Implementations of SHA-3 Candidates on FPGAs |
scientific article |
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Lightweight Implementations of SHA-3 Candidates on FPGAs (English)
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16 December 2011
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SHA-3
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FPGA
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lightweight implementation
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benchmarking
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