Verification of a multiprocessor cache protocol using simulation relations and higher-order logic (Q685110): Difference between revisions
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| Property / cites work: The existence of refinement mappings / rank | |||
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| Property / cites work: Automatic Verification of Sequential Circuits Using Temporal Logic / rank | |||
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Latest revision as of 08:38, 30 July 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | Verification of a multiprocessor cache protocol using simulation relations and higher-order logic |
scientific article |
Statements
Verification of a multiprocessor cache protocol using simulation relations and higher-order logic (English)
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30 September 1993
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