VLSI architectures for sliding-window-based space-time turbo Trellis code decoders (Q693833): Difference between revisions
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Latest revision as of 23:10, 5 July 2024
scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| English | VLSI architectures for sliding-window-based space-time turbo Trellis code decoders |
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VLSI architectures for sliding-window-based space-time turbo Trellis code decoders (English)
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11 December 2012
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Summary: The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO) unit, A-, B-, \(\Gamma\)-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.
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