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  • Date of Publication Type Design of QPP Interleavers for the Parallel Turbo Decoding Architecture 2021-08-26 Paper...
    10 bytes (13 words) - 21:29, 26 December 2023
  • Date of Publication Type Design of QPP Interleavers for the Parallel Turbo Decoding Architecture 2021-08-26 Paper Fixed-Point Analysis and Parameter Optimization...
    10 bytes (13 words) - 14:11, 24 September 2023
  • networks 2023-09-29 Paper Design of QPP Interleavers for the Parallel Turbo Decoding Architecture 2021-08-26 Paper Fixed-Point Analysis and Parameter Optimization...
    10 bytes (14 words) - 09:48, 6 October 2023
  • Algebraic Soft-Decision Reed–Solomon Decoding 2021-08-26 Paper Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes 2021-08-26...
    10 bytes (13 words) - 17:12, 24 September 2023
  • Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis 2021-08-26 Paper Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic...
    10 bytes (13 words) - 03:21, 28 December 2023
  • 2016-09-16 Paper Parallel reconfigurable decoder architectures for rotation LDPC codes 2013-10-18 Paper Using linear programming to decode LDPC codes 2011-08-05...
    10 bytes (14 words) - 07:41, 7 October 2023
  • Type Improved parallel weighted bit-flipping decoding algorithm for {LDPC} codes 2013-10-18 Paper Parallel reconfigurable decoder architectures for rotation...
    10 bytes (14 words) - 17:03, 21 September 2023
  • ad hoc networks 2006-09-12 Paper Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm 2005-11-16...
    10 bytes (15 words) - 22:24, 8 December 2023
  • Instruction Level Parallel Architectures 2018-07-09 Paper Cross-layer power management in wireless networks and consequences on system-level architecture 2009-10-29...
    10 bytes (13 words) - 06:14, 13 December 2023
  • multiple antennas 2006-09-12 Paper Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm 2005-11-16...
    10 bytes (17 words) - 17:13, 13 December 2023
  • low-area low-power parallel FIR filter design 2005-05-03 Paper Interleaved convolutional code and its Viterbi decoder architecture 2005-05-03 Paper Low-complexity...
    10 bytes (17 words) - 17:13, 13 December 2023
  • OFDM-Based RadCom Systems 2022-09-23 Paper On Decoding Binary Quasi-Reversible BCH Codes 2022-07-13 Paper On Decoding Algebraic Codes Using Radical Locators 2020-12-04...
    10 bytes (15 words) - 08:45, 9 December 2023
  • Paper High-speed \(\mathrm{RS}(255, 239)\) decoder based on LCC decoding 2012-04-04 Paper Efficient bit-parallel multipliers over finite fields GF\((2^m)\)...
    10 bytes (15 words) - 20:27, 11 December 2023
  • 1993-12-12 Paper A VLSI architecture for simplified arithmetic Fourier transform algorithm 1992-09-27 Paper The algebraic decoding of the (41, 21, 9) quadratic...
    10 bytes (17 words) - 08:45, 9 December 2023
  • Multiple Stream Decoding of Cortex Codes 2018-07-18 Paper Delayed Stochastic Decoding of LDPC Codes 2018-07-18 Paper Stochastic Decoding of Turbo Codes...
    10 bytes (15 words) - 07:27, 7 October 2023
  • Designed Architecture-Aware LDPC Convolutional Codes and High-Throughput Parallel Encoders/Decoders 2021-08-26 Paper An Efficient Parallel Architecture for...
    10 bytes (15 words) - 08:08, 7 October 2023
  • Interleaver for Clockless Fully Parallel LDPC Decoding 2021-08-26 Paper Relaxation Dynamics in Stochastic Iterative Decoders 2018-07-09 Paper Cooperative...
    10 bytes (14 words) - 11:56, 7 October 2023
  • 2021-08-26 Paper An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems 2017-10-30 Paper A Unified Architecture for the Accurate and High-Throughput...
    10 bytes (13 words) - 08:08, 7 October 2023
  • Spatially Correlated Interference Packet Networks 2019-01-28 Paper PETRELS: Parallel Subspace Estimation and Tracking by Recursive Least Squares From Partial...
    10 bytes (15 words) - 22:29, 11 December 2023
  • Paper PACT XPP -- a self-reconfigurable data processing architecture 2004-03-15 Paper VLSI architecture of modified Euclidean algorithm for Reed-Solomon code...
    10 bytes (12 words) - 12:30, 24 September 2023