Maximum ease of testability of logic circuits with respect to multiple stuck-on faults

DOI10.1007/BF01125126zbMath0875.94150MaRDI QIDQ1816073

N. D. Stukach

Publication date: 18 December 1996

Published in: Cybernetics and Systems Analysis (Search for Journal in Brave)

zbMATH Keywords

synthesisabstract finite automatonmultiple stuck-on faultstestability of logic circuits

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Fault detection; testing in circuits and networks (94C12)

Cites Work

• On Minimally Testable Logic Networks

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