A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention (Q2267141)

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A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention
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    A parameterized multilevel pattern matching architecture on FPGAs for network intrusion detection and prevention (English)
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    26 February 2010
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    network intrusion detection
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    network intrusion prevention
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    pattern matching
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    network security
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