Pages that link to "Item:Q5655292"
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The following pages link to Easily Testable Realizations ror Logic Functions (Q5655292):
Displayed 26 items.
- Algorithms for conversion of minterms to positive polarity Reed-Muller coefficients and vice versa (Q287075) (← links)
- A method for synthesis of easily-testable circuits in some basis admitting single fault detection tests of constant length (Q355292) (← links)
- Single fault detection tests for circuits of functional elements (Q469094) (← links)
- Power minimization of FPRM functions based on polarity conversion (Q1415935) (← links)
- Lower bounds for the lengths of single tests for Boolean circuits (Q1741479) (← links)
- A method of synthesis of irredundant circuits admitting single fault detection tests of constant length (Q1741482) (← links)
- Short single tests for circuits with arbitrary stuck-at faults at outputs of gates (Q2332897) (← links)
- Unit checking output tests under constant faults for functional elements (Q2513254) (← links)
- Families of Reed-Muller canonical forms (Q3202953) (← links)
- Invited paper. Boolean matrix representation for the conversion of minterms to Reed–Muller coefficients and the minimization of Exclusive-OR switching functions (Q3479986) (← links)
- Simplified theory of boolean functions (Q3481651) (← links)
- New dimensions in non‐classical neural computing, part II: quantum, nano, and optical (Q3639474) (← links)
- Circuits for<i>m</i>‐valued classical, reversible and quantum optical computing with application to regular logic design (Q3639478) (← links)
- New dimensions in non‐classical neural computing (Q3639490) (← links)
- Ring testing of discrete devices implementing polynomtal forms (Q3798605) (← links)
- Check of linear combination circuits (Q3887351) (← links)
- Structure of modulo-2 ring-sum canonical expansions for boolean functions (Q3990957) (← links)
- Short single fault detection tests for logic networks under arbitrary faults of gates (Q5071224) (← links)
- On the relation between BDDs and FDDs (Q5096325) (← links)
- SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES (Q5151082) (← links)
- Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates (Q5151257) (← links)
- On the exact value of the length of the minimal single diagnostic test for a particular class of circuits (Q5374004) (← links)
- Multiple-level circuit solutions to the circuit non-decomposability problem of the set-theoretic modified reconstructability analysis (MRA) (Q5443485) (← links)
- Optimization of fixed-polarity Reed-Muller circuits using dual-polarity property (Q5928981) (← links)
- Short complete diagnostic tests for circuits with two additional inputs in some basis (Q6051966) (← links)
- Shannon function of the test length with respect to gate input identification (Q6195911) (← links)