A neural network accelerated optimization method for FPGA

DOI10.1007/S10878-024-01117-XMaRDI QIDQ6645179zbMATH OpenFDO

Authors Zhengwei Hu, Sijie Zhu, Leilei Wang, Wangbin Cao, Zhiyuan Xie

Publication date 28 November 2024

Published in Journal of Combinatorial Optimization (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/S10878-024-01117-X

zbMATH Keywords

field programmable gate arrayhardware accelerationhigh-level synthesisMitchell algorithmneural network

Mathematics Subject Classification ID

Mathematical programming (90Cxx)

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Cites work

• Exploring the Design Space of Fair Scheduling Supports for Asymmetric Multicore Systems
• Neural network approximation: three hidden layers are enough
• Probabilistic robustness estimates for feed-forward neural networks

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