A realistic study on multithreaded superscalar processor design

DOI10.1007/BFB0002858MaRDI QIDQ4537099zbMATH OpenFDO

Authors Yuan C. Chou, Daniel Paul Siewiorek, John P. Shen

Publication date 25 June 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BFB0002858

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Computing methodologies and applications (68U99)

Recommendations

• Multithreaded Processors
• Applying Formal Methods: Testing, Performance, and M/E-Commerce
• Adaptive dynamic thread scheduling for simultaneous multithreaded architectures with a detector thread
• scientific article; zbMATH DE number 1543060
• Dual-thread speculation: A simple approach to uncover thread-level parallelism on a simultaneous multithreaded processor

Cited in

(20)

• Supporting microthread scheduling and synchronisation in CMPs
• Adaptive dynamic thread scheduling for simultaneous multithreaded architectures with a detector thread
• scientific article; zbMATH DE number 986147 (Why is no real title available?)
• HIGH SPEED SYNCHRONIZATION FOR A STATICALLY SCHEDULED SUPERSCALAR PROCESSOR
• Multithreading for logic-centric systems
• scientific article; zbMATH DE number 2080132 (Why is no real title available?)
• scientific article; zbMATH DE number 2080882 (Why is no real title available?)
• scientific article; zbMATH DE number 1543060 (Why is no real title available?)
• scientific article; zbMATH DE number 1543368 (Why is no real title available?)
• scientific article; zbMATH DE number 1543371 (Why is no real title available?)
• Multithreaded Processors
• Fine-grained multithreading on the CRAY T3E
• Simultaneous Multithreading Applied to Real Time
• EVALUATION OF THE HYPER‐THREADING TECHNOLOGY FOR HEAT CONDUCTION‐TYPE PROBLEMS
• ChunkedTejas: a chunking-based approach to parallelizing a trace-driven architectural simulator
• A case for chip multiprocessors based on the data-driven multithreading model
• Dynamic instruction scheduling in a trace-based multi-threaded architecture
• Dual-thread speculation: A simple approach to uncover thread-level parallelism on a simultaneous multithreaded processor
• The impact of speculative execution on SMT processors
• A spatially triggered dissipative resource distribution policy for SMT processors

This page was built for publication: A realistic study on multithreaded superscalar processor design

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4537099)