Admission control in shared memory switches
From MaRDI portal
Recommendations
- Essential traffic parameters for shared memory switch performance
- Competitive buffer management for shared-memory switches
- Harmonic buffer management policy for shared memory switches
- Performance and fluid simulations of a novel shared buffer management system
- Optimum Scheduling and Memory Management in Input Queued Switches With Finite Buffer Space
Cites work
- scientific article; zbMATH DE number 1232130 (Why is no real title available?)
- An improved algorithm for CIOQ switches
- Best effort and priority queuing policies for buffered crossbar switches
- Buffer Management in a Packet Switch
- Buffer Overflow Management in QoS Switches
- Competitive buffer management for shared-memory switches
- Competitive queue policies for differentiated services
- Essential traffic parameters for shared memory switch performance
- FIFO queueing policies for packets with heterogeneous processing
- Harmonic buffer management policy for shared memory switches
- Improved competitive performance bounds for CIOQ switches
- Lower and upper bounds on FIFO buffer management in QoS switches
- MMPP models for multimedia traffic
- Maximizing throughput in multi-queue switches
- On the Performance of Greedy Algorithms in Packet Buffering
- Optimal smoothing schedules for real-time streams
- Packet mode and QoS algorithms for buffered crossbar switches with FIFO queuing
This page was built for publication: Admission control in shared memory switches
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q2317132)