An analytical model for Network-on-Chip with finite input buffer

DOI10.1007/S11704-010-0117-0MaRDI QIDQ352048zbMATH OpenOpenAlexFDO

Authors Yu-Bai Li, Chang Wu, Jian Wang

Publication date 4 July 2013

Published in Frontiers of Computer Science in China (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/s11704-010-0117-0

zbMATH Keywords

analytical modelfinite bufferNetwork-on-Chip (NoC)queue system

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

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Cites work

• Analysis of a tandem network model of a single-router network-on-chip
• scientific article; zbMATH DE number 4068014 (Why is no real title available?)
• scientific article; zbMATH DE number 50893 (Why is no real title available?)
• Network calculus. A theory of deterministic queueing systems for the Internet

Cited in

(5)

• A high level power model for network-on-chip (NoC) router
• Buffer planning for application-specific networks-on-chip design
• Analysis of the input to a buffer storage in front of a packet switch
• Real-time analysis of priority-preemptive NoCs with arbitrary buffer sizes and router delays
• Analysis of a tandem network model of a single-router network-on-chip

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