Automatic implementation of affine iterative algorithms: Design flow and communication synthesis
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Cites work
- A comparison of clustering heuristics for scheduling directed acyclic graphs on multiprocessors
- A LIBRARY FOR DOING POLYHEDRAL OPERATIONS
- A unifying lattice-based approach for the partitioning of systolic arrays via LPGS and LSGP
- APEmille
- Dataflow analysis of array and scalar references
- Geometrical tools to map systems of affine recurrence equations on regular arrays
- scientific article; zbMATH DE number 5995471 (Why is no real title available?)
- scientific article; zbMATH DE number 4070258 (Why is no real title available?)
- scientific article; zbMATH DE number 4089320 (Why is no real title available?)
- scientific article; zbMATH DE number 42110 (Why is no real title available?)
- scientific article; zbMATH DE number 1760022 (Why is no real title available?)
- The parallel execution of DO loops
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