Charge-mode parallel architecture for vector-matrix multiplication

DOI10.1109/82.974781MaRDI QIDQ4553223zbMATH OpenOpenAlexFDO

Authors Roman Genov, Gert Cauwenberghs

Publication date 25 November 2002

Published in IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/82.974781

zbMATH Keywords

analog array processorsanalog-to-digital conversion (ADC)charge-injection device (CID)dynamic random-access memory (DRAM)support vector machines (SVM)vector quantization (VQ)vector-matrix multiplication (VMM)

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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Cited in

(1)

• Vector-matrix multiplication in ternary optimal computer

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