Complexity and synthesis of minimal logic circuits using multiplexers

DOI10.1007/BF01131861MaRDI QIDQ1816349zbMATH OpenFDO

Authors V. I. Lazarev

Publication date 20 January 1997

Published in Cybernetics and Systems Analysis (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/BF01131861

zbMATH Keywords

combinational networklogic circuitsmultiplexer formulas

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cited in

(6)

• Minimal feedforward parity networks using threshold gates
• scientific article; zbMATH DE number 5129255 (Why is no real title available?)
• Minimum Universal Logic Module Sequential Circuits with Decoders
• ULM Implicants for Minimization of Univers Logic Module Circuits
• scientific article; zbMATH DE number 1737504 (Why is no real title available?)
• scientific article; zbMATH DE number 2107115 (Why is no real title available?)

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