Minimum Universal Logic Module Sequential Circuits with Decoders

DOI10.1109/TC.1977.1674741MaRDI QIDQ4140883zbMATH OpenOpenAlexFDO

Authors R. P. Voith

Publication date 1977

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1977.1674741

Mathematics Subject Classification ID

Formal languages and automata (68Q45)

Recommendations

• scientific article; zbMATH DE number 3926812
• ULM Implicants for Minimization of Univers Logic Module Circuits
• Logic design of decoded-programmable logic arrays
• Complexity and synthesis of minimal logic circuits using multiplexers
• scientific article; zbMATH DE number 1285548
• scientific article; zbMATH DE number 4047614
• Minimal parallel prefix circuits
• scientific article; zbMATH DE number 3257831
• Logical modulo test circuits: Their design in unitary positional binary codes

Cited in

(5)

• scientific article; zbMATH DE number 3900681 (Why is no real title available?)
• scientific article; zbMATH DE number 3900682 (Why is no real title available?)
• ULM Implicants for Minimization of Univers Logic Module Circuits
• scientific article; zbMATH DE number 3570350 (Why is no real title available?)
• scientific article; zbMATH DE number 3621639 (Why is no real title available?)

This page was built for publication: Minimum Universal Logic Module Sequential Circuits with Decoders

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4140883)