Logic design of decoded-programmable logic arrays

DOI10.1080/00207219008920316MaRDI QIDQ3489955zbMATH OpenOpenAlexFDO

Authors Yongxin Xiao

Publication date 1990

Published in International Journal of Electronics (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/00207219008920316

zbMATH Keywords

Decoded-programmable logic arraysminimization of OR-AND-OR expression of boolean functions

Mathematics Subject Classification ID

Recommendations

• Function symmetries and decoded-PLA realization
• Input Variable Assignment and Output Phase Optimization of PLA's
• scientific article; zbMATH DE number 3939260
• A New Approach to the Design of Testable PLA's
• scientific article; zbMATH DE number 862271

Cites work

• A Way to Simplify Truth Functions
• High-Speed Programmable Logic Array Adders
• MINI: A Heuristic Approach for Logic Minimization
• Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

Cited in

(10)

• Generation of symbolic layout in one-dimensional logic array
• Function symmetries and decoded-PLA realization
• Multilevel programmable logic array schemes for microprogrammed automata
• 5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs
• Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach
• Input Variable Assignment and Output Phase Optimization of PLA's
• scientific article; zbMATH DE number 4021028 (Why is no real title available?)
• Minimum Universal Logic Module Sequential Circuits with Decoders
• scientific article; zbMATH DE number 1045473 (Why is no real title available?)
• scientific article; zbMATH DE number 862271 (Why is no real title available?)

This page was built for publication: Logic design of decoded-programmable logic arrays

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3489955)