Generation of symbolic layout in one-dimensional logic array

DOI10.1016/0010-4485(88)90007-3MaRDI QIDQ1109793zbMATH OpenOpenAlexFDO

Authors S. H. Smith

Publication date 1988

Published in CAD. Computer-Aided Design (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0010-4485(88)90007-3

zbMATH Keywords

complete graphnetlisttrackscolumnsone-dimensional arraysoverriding property

Mathematics Subject Classification ID

Graph theory (05C99)

Recommendations

• scientific article; zbMATH DE number 811541
• An Array Layout Methodology for VLSI Circuits
• scientific article; zbMATH DE number 4110154
• Logic design of decoded-programmable logic arrays
• Logic Synthesis for Switching Lattices
• scientific article; zbMATH DE number 3351431

Cited in

(2)

• Algorithm for embedding logic networks in uniform arrays
• Distributed algorithms for maximum cliques

This page was built for publication: Generation of symbolic layout in one-dimensional logic array

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q1109793)