Input Variable Assignment and Output Phase Optimization of PLA's

DOI10.1109/TC.1984.1676349MaRDI QIDQ3337381zbMATH OpenFDO

Authors Tsutomu Sasao

Publication date 1984

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1984.1676349

zbMATH Keywords

arithmetic functionscomplexity of logic circuitscontrol circuitsdecoder assignmentessential prime implicants detectioninput variable assignmentlogic designoutput phase assignmentPLA minimization systemprogrammable logic array

Mathematics Subject Classification ID

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(9)

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Describes a project that uses

Uses Software

• ESPRESSO

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