Dual-Mode Logic for Function-Independent Fault Testing

DOI10.1109/TC.1980.1675500MaRDI QIDQ3893850zbMATH OpenOpenAlexFDO

Authors Sumit Dasgupta, Carlos R. P. Hartmann, Luther D. Rudolph

Publication date 1980

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tc.1980.1675500

zbMATH Keywords

dual-mode combinational logic networkdual-mode sequential logic networkfault testingfunction-independent testsstuck-at-faults

Mathematics Subject Classification ID

Cited in

(6)

• A method of synthesis of irredundant circuits admitting single fault detection tests of constant length
• Lower bound of the length of a single fault diagnostic test with respect to insertions of a mod-2 adder
• Complete fault detection tests of length 2 for logic networks under stuck-at faults of gates
• Short Complete Fault Detection Tests for Logic Networks with Fan-In Two
• On the exact value of the length of the minimal single diagnostic test for a particular class of circuits
• The length of a single fault detection test for constant-nonpreserving element insertions

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