Efficient Embeddings of Binary Trees in VLSI Arrays

DOI10.1109/TC.1987.5009532MaRDI QIDQ3786430zbMATH OpenFDO

Authors Dan Gordon

Publication date 1987

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.1987.5009532

zbMATH Keywords

area-efficient embeddingarrays of processing elementsbinary tree layoutgraph embeddinginterconnection networkVLSI

Mathematics Subject Classification ID

Planar graphs; geometric and topological aspects of graph theory (05C10) Analysis of algorithms and problem complexity (68Q25) Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15)

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• Embedding ternary trees in VLSI arrays
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• Algorithm for embedding logic networks in uniform arrays
• Expansion of layouts of complete binary trees into grids
• An optimal emulator and VLSI layout for complete binary trees
• Embeddings of complete binary trees into grids and extended grids with total vertex-congestion 1
• Separator-based graph embedding into multidimensional grids with small edge-congestion
• scientific article; zbMATH DE number 3864518 (Why is no real title available?)
• Planar straight-line embedding of double-tree ccan architecture on a rectangular grid
• Minced trees, with applications to fault-tolerant VLSI processor arrays

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