Efficient hardware implementation of elliptic curve cryptosystems
From MaRDI portal
Recommendations
Cited in
(21)- Efficient cryptography on the RISC-V architecture
- On efficient implementation of FPGA-based hyperelliptic curve cryptosystems
- Implementation of high speed arithmetic point production model for elliptic curve engine
- scientific article; zbMATH DE number 1618062 (Why is no real title available?)
- Ultra high-performance ASIC implementation of SM2 with SPA resistance
- Full-custom VLSI design of a unified multiplier for elliptic curve cryptography on RFID tags
- scientific article; zbMATH DE number 6001033 (Why is no real title available?)
- Fast Elliptic-Curve Cryptography on the Cell Broadband Engine
- scientific article; zbMATH DE number 1979296 (Why is no real title available?)
- scientific article; zbMATH DE number 2044537 (Why is no real title available?)
- scientific article; zbMATH DE number 2048542 (Why is no real title available?)
- scientific article; zbMATH DE number 2058638 (Why is no real title available?)
- scientific article; zbMATH DE number 2143950 (Why is no real title available?)
- Development of Fast Multiplier Structures with Cryptographic Applications
- High-Performance Interface Architectures for Cryptographic Hardware
- Efficient hardware implementations of brw polynomials and tweakable enciphering schemes
- VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors
- Hardware design issues in elliptic curve cryptography for wireless systems
- Efficient elliptic curve cryptographic hardware design for wireless security
- Topics in Cryptology – CT-RSA 2004
- Efficient hardware implementation of finite fields with applications to cryptography
This page was built for publication: Efficient hardware implementation of elliptic curve cryptosystems
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3421461)