FOLDING TRANSFORMATIONS ON SYSTOLIC AND VLSI PROCESSOR ARRAYS

DOI10.1080/10637199408915467MaRDI QIDQ4820052zbMATH OpenOpenAlexFDO

Authors M. Gušev, D. J. Evans

Publication date 6 October 2004

Published in Parallel Algorithms and Applications (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1080/10637199408915467

Mathematics Subject Classification ID

Numerical algorithms for specific classes of architectures (65Y10) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites work

• scientific article; zbMATH DE number 3628373 (Why is no real title available?)
• Implementation of folding transformations on linear VSLI processor arrays
• On the Analysis and Synthesis of VLSI Algorithms
• Triangular systolic arrays for matrix product and factorisation

Cited in

(1)

• THE MAGIC OF INTERLOCKING PROPERTY: FAST SYSTOLIC DESIGN

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