FPGA logic synthesis using quantified Boolean satisfiability

DOI10.1007/11499107_37MaRDI QIDQ5713741zbMATH OpenOpenAlexFDO

Authors Andrew Ling, Deshanand P. Singh, Stephen D. Brown

Publication date 15 December 2005

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1007/b137280

Mathematics Subject Classification ID

Problem solving in the context of artificial intelligence (heuristics, search strategies, etc.) (68T20)

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Cited in

(11)

• A solver for QBFs in negation normal form
• Lower bound techniques for QBF expansion
• Building strategies into QBF proofs
• Symbolic system synthesis using answer set programming
• 5 Logic Synthesis Method of Digital Circuits Designed for Implementation with Embedded Memory Blocks of FPGAs
• scientific article; zbMATH DE number 7228403 (Why is no real title available?)
• FPGA design automation: a survey
• Designing an Efficient Hardware Implication Accelerator for SAT Solving
• Generating test patterns for FPGA circuits: a quantum computing approach
• Building strategies into QBF proofs
• Correct Hardware Design and Verification Methods

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Uses Software

• Chaff
• Quaffle

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