Run-time performance optimization of an FPGA-based deduction engine for SAT solvers

DOI10.1007/3-540-44687-7_33MaRDI QIDQ4786132zbMATH OpenFDO

Authors Andreas Dandalis, Bharani Thiruvengadam, V. K. Prasanna Kumar

Publication date 12 December 2002

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2147/21470315

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07) Logic in artificial intelligence (68T27) Computing methodologies and applications (68U99)

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(7)

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• Implementing CSAT local search on FPGAs
• Correct Hardware Design and Verification Methods
• FPGA logic synthesis using quantified Boolean satisfiability

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