Implementing CSAT local search on FPGAs

DOI10.1007/3-540-46117-5_130MaRDI QIDQ4408321zbMATH OpenFDO

Authors Martin Henz, Edgar Tan, Roland H. C. Yap

Publication date 29 June 2003

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2438/24381156.htm

Mathematics Subject Classification ID

Computing methodologies and applications (68U99)

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Cited in

(7)

• Hybrid routing for FPGAs by integrating Boolean satisfiability with geometric search
• One flip per clock cycle
• FM SCREENING BY THE LOCAL EXHAUSTIVE SEARCH, WITH HARDWARE ACCELERATION
• Run-time performance optimization of an FPGA-based deduction engine for SAT solvers
• Parallelizing local search for CNF satisfiability using vectorization and PVM
• Quantitative analysis of FPGA-based database searching
• Towards optimized and constant-time CSIDH on embedded devices

Describes a project that uses

Uses Software

• Walksat

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