One flip per clock cycle

DOI10.1007/3-540-45578-7_35MaRDI QIDQ4475656zbMATH OpenFDO

Authors Martin Henz, Edgar Tan, Roland H. C. Yap

Publication date 9 August 2004

Published in Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL http://link.springer.de/link/service/series/0558/bibs/2239/22390509.htm

Mathematics Subject Classification ID

Problem solving in the context of artificial intelligence (heuristics, search strategies, etc.) (68T20)

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(5)

• FPGA implementation of a stochastic neural network for monotonic pseudo-Boolean optimization
• A SAT solver using reconfigurable hardware and virtual logic
• A SAT solver using reconfigurable hardware and virtual logic
• Hybrid routing for FPGAs by integrating Boolean satisfiability with geometric search
• Accelerating a continuous-time analog SAT solver using GPUs

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