Formal modeling and verification of microprocessors
From MaRDI portal
Recommendations
Cited in
(32)- The notion of proof in hardware verification
- Formal verification of a complex pipelined processor
- Modular deductive verification of multiprocessor hardware designs
- Algebraic models of microprocessors architecture and organisation
- Specifying the Caltech asynchronous microprocessor
- An Isabelle/HOL formalisation of the SPARC instruction set architecture and the TSO memory model
- scientific article; zbMATH DE number 1670752 (Why is no real title available?)
- scientific article; zbMATH DE number 1670784 (Why is no real title available?)
- scientific article; zbMATH DE number 1701763 (Why is no real title available?)
- scientific article; zbMATH DE number 4018390 (Why is no real title available?)
- The use of hoare logic in the verification of horizontal microprograms
- Advanced automation in formal verification of processors.
- scientific article; zbMATH DE number 4039272 (Why is no real title available?)
- scientific article; zbMATH DE number 46617 (Why is no real title available?)
- Automated proofs of object code for a widely used microprocessor
- scientific article; zbMATH DE number 1107561 (Why is no real title available?)
- scientific article; zbMATH DE number 1487483 (Why is no real title available?)
- Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics
- scientific article; zbMATH DE number 2102697 (Why is no real title available?)
- Design and verification of microprocessor systems for high-assurance applications
- Computer Aided Verification
- Verification: industrial applications
- Algebra and Coalgebra in Computer Science
- Correct Hardware Design and Verification Methods
- Correct Hardware Design and Verification Methods
- Computer Aided Verification
- Algebraic models of correctness for microprocessors
- Efficient simulation of formal processor models
- A formalisation of \textsc{xMAS}
- Formal verification of arithmetic RTL: translating Verilog to C++ to ACL2
- Silicon debug of a powerPC microprocessor using model checking
- A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessor
This page was built for publication: Formal modeling and verification of microprocessors
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4419604)