Graph-based techniques to speed up floorplan area optimization

DOI10.1016/0167-9260(93)90051-DMaRDI QIDQ4307639zbMATH OpenOpenAlexFDO

Authors Ting-Chi Wang, D. F. Wong

Publication date 20 March 1995

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-9260(93)90051-d

zbMATH Keywords

constrained shortest pathfloorplan area optimizationfloorplan design

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Applications of graph theory to circuits and networks (94C15)

Recommendations

• Trees, slices, and wheels: On the floorplan area minimization problem
• Optimal module sizing in VLSI floorplanning by nonlinear programming
• Compact floor-planning via orderly spanning trees
• Floorplan design of VLSI circuits
• An optimal algorithm for layered wheel floorplan designs

Cited in

(5)

• An attractor-repeller approach to floorplanning
• A quasi-Newton-based floorplanner for fixed-outline floorplanning
• An optimal algorithm for layered wheel floorplan designs
• Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization
• Technology mapping for area and speed

This page was built for publication: Graph-based techniques to speed up floorplan area optimization

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4307639)