High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform

DOI10.1109/TSP.2007.900754MaRDI QIDQ4567638zbMATH OpenOpenAlexFDO

Authors Chao Cheng, Keshab K. Parhi

Publication date 27 June 2018

Published in IEEE Transactions on Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tsp.2007.900754

Mathematics Subject Classification ID

Nontrigonometric harmonic analysis involving wavelets and other special systems (42C40) Numerical methods for wavelets (65T60) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

Cited in

(3)

• High-performance 1-D and 2-D inverse DWT 5/3 filter architectures for efficient hardware implementation
• A novel FPGA architecture of a 2-D wavelet transform
• scientific article; zbMATH DE number 1880856 (Why is no real title available?)

This page was built for publication: High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q4567638)