Hough transform algorithm for FPGA implementation.
In this paper a novel algorithm for computing the Hough transform is introduced. The basic idea consists in using a combination of an incremental method with the usual Hough transform expression to join circuit performances and accuracy requirements. The algorithm is primarily developed to fit field programmable gate arrays (FPGA) implementation that have become a competitive alternative for high-performance digital signal processing applications. The induced architecture presents a high degree of regularity, making its VLSI implementation very straightforward. This implementation may be achieved by generator program, assuring a shorter design cycle and a lower cost. For illustration, implementation results of 8-bit image pixels is given.
- Real-time CAM-based Hough transform algorithm and its performance evaluation.
- Efficient implementation of fast Hough transform using CPCA coprocessor
- A VLSI array architecture for Hough transform
- Deriving ASIC architectures for the Hough transform
- A parallel Hough transform algorithm for nonuniform images
- Real-time CAM-based Hough transform algorithm and its performance evaluation.
- FPGA implementation of a geometric voting scheme for the extraction of geometric entities from images
- Efficient implementation of fast Hough transform using CPCA coprocessor
- scientific article; zbMATH DE number 1941123 (Why is no real title available?)
- Accurate and Real-time Image Processing on a New PC-compatible Board
- A VLSI array architecture for Hough transform
- Deriving ASIC architectures for the Hough transform
This page was built for publication: Hough transform algorithm for FPGA implementation.
Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q5941328)
