Implementation of a communications channelizer using FPGAs and RNS arithmetic

DOI10.1023/A:1008167323437MaRDI QIDQ5943330zbMATH OpenFDO

Authors Uwe Meyer-Bäse, Antonio García, Fred Taylor

Publication date 10 September 2002

Published in Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1023/A:1008167323437

zbMATH Keywords

digital signal processingfield-programmable logic

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

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