Data communication in parallel architectures (Q1823645)

From MaRDI portal
!
WARNING

This is the item page for this Wikibase entity, intended for internal use and editing purposes.

Please use the normal view instead:

scientific article; zbMATH DE number 4115916
Language Label Description Also known as
default for all languages
No label defined
    English
    Data communication in parallel architectures
    scientific article; zbMATH DE number 4115916

      Statements

      Data communication in parallel architectures (English)
      0 references
      0 references
      0 references
      1989
      0 references
      Timing estimates for various forms of data exchange in a variety of parallel architectures are investigated. Data exchange methods emphasized are: one to one, one to all, all to all, scatter, and multiscatter. Parallel architectures, emphasized are: bus, shared memory, ring, grid, hypercube and switch. Tables summarizing the timing estimates are given.
      0 references
      parallel computer
      0 references
      interprocessor communication
      0 references
      Data exchange
      0 references

      Identifiers