Data communication in parallel architectures

DOI10.1016/0167-8191(89)90024-0MaRDI QIDQ1823645zbMATH OpenOpenAlexFDO

Authors Y. Saad, Martin H. Schultz

Publication date 1989

Published in Parallel Computing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/0167-8191(89)90024-0

zbMATH Keywords

Data exchangeinterprocessor communicationparallel computer

Mathematics Subject Classification ID

Theory of operating systems (68N25) Theory of software (68N99)

Review text

Timing estimates for various forms of data exchange in a variety of parallel architectures are investigated. Data exchange methods emphasized are: one to one, one to all, all to all, scatter, and multiscatter. Parallel architectures, emphasized are: bus, shared memory, ring, grid, hypercube and switch. Tables summarizing the timing estimates are given.

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• Parallel data processing in computer networks
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• Communication complexity of fault-tolerant information diffusion
• Scheduling a divisible task in a two-dimensional toroidal mesh
• Optimal data exchange algorithms on star graphs
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