Field-programmable logic and applications. Reconfigurable computing is going mainstream. 12th international conference, FPL 2002, Montpellier, France, September 2--4, 2002. Proceedings (Q1866720)

The articles of this volume will be reviewed individually. The preceding conference has been reviewed (see Zbl 0972.68764). Indexed articles: \textit{Master, Paul}, The age of adaptive computing is here, 1-3 [Zbl 1020.68797] \textit{Hartenstein, Reiner W.}, Disruptive trends by data-stream-based computing, 4 [Zbl 1020.68657] \textit{Brebner, Gordon}, Multithreading for logic-centric systems, 5-14 [Zbl 1020.68558] \textit{Sarmadi, Siavash Bayat; Miremadi, Seyed Ghassem; Asadi, Ghazanfar; Ejlali, Ali Reza}, Fast prototyping with co-operation of simulation and emulation, 15-25 [Zbl 1020.68877] \textit{Krupnova, Helena; Meurou, Veronique; Barnichon, Christophe; Serra, Carlos; Morsi, Farid}, How fast is rapid FPGA-based prototyping: Lessons and challenges from the digital TV design prototyping project, 26-35 [Zbl 1020.68747] \textit{Ho, Quoc Thai; Rigaud, Jean-Baptiste; Fesquet, Laurent; Renaudin, Marc; Rolland, Robin}, Implementing asynchronous circuits on LUT based FPGAs, 36-46 [Zbl 1020.68671] \textit{Di Martino, Beniamino; Mazzocca, Nicola; Saggese, Giacinto Paolo; Strollo, Antonio G. M.}, A technique for FPGA synthesis driven by automatic source code analysis and transformations, 47-58 [Zbl 1020.68610] \textit{Compton, Katherine; Sharma, Akshay; Phillips, Shawn; Hauck, Scott}, Flexible routing architecture generation for domain-specific reconfigurable subsystems, 59-68 [Zbl 1020.68597] \textit{Khan, Jawad; Handa, Manish; Vemuri, Ranga}, iPACE-V1: A portable adaptive computing engine for real time applications, 69-78 [Zbl 1020.68713] \textit{Sima, Mihai; Vassiliadis, Stamatis; Cotofana, Sorin; van Eijndhoven, Jos T. J.; Vissers, Kees}, Field-programmable custom computing machines --- A taxonomy, 79-88 [Zbl 1020.68892] \textit{Leijten-Nowak, Katarzyna; van Meerbergen, Jef L.}, Embedded reconfigurable logic core for DSP applications, 89-101 [Zbl 1020.68760] \textit{Cardells-Tormo, Francisco; Valls-Coquillat, Javier; Almenar-Terre, Vicenc; Torres-Carot, Vicente}, Efficient FPGA-based QPSK demodulation loops: Application to the DVB standard, 102-111 [Zbl 1020.68571] \textit{Dick, Chris; Harris, Fred}, FPGA QAM demodulator design, 112-121 [Zbl 1020.68611] \textit{Lemieux, Guy G.; Lewis, David M.}, Analytical framework for switch block design, 122-131 [Zbl 1020.68762] \textit{Koorapaty, Aneesh; Pileggi, Lawrence}, Modular, fabric-specific synthesis for programmable architectures, 132-141 [Zbl 1020.68737] \textit{Fan, Hongbing; Liu, Jiping; Wu, Yu-Liang; Cheung, Chak-Chung}, On optimum designs of universal switch blocks, 142-151 [Zbl 1020.68622] \textit{Robertson, Ian; Irvine, James; Lysaght, Patrick; Robinson, David}, Improved functional simulation of dynamically reconfigurable logic, 152-161 [Zbl 1020.68863] \textit{Lopez-Buedo, S.; Riviere, P.; Pernas, P.; Boemo, E.}, Run-time reconfiguration to check temperature in custom computers: An application of JBits technology, 162-170 [Zbl 1020.68779] \textit{Smit, Gerard J. M.; Havinga, Paul J. M.; Smit, Lodewijk T.; Heysters, Paul M.; Rosien, Michel A. J.}, Dynamic reconfiguration in mobile systems, 171-181 [Zbl 1020.68894] \textit{Horta, Edson L.; Lockwood, John W.; Kofuji, Sérgio T.}, Using PARBIT to implement partial run-time reconfigurable systems, 182-191 [Zbl 1020.68673] \textit{Turner, R. H.; Woods, R.; Courtney, T.}, Multiplier-less realization of a poly-phase filter using lUT-based FPGAs, 192-201 [Zbl 1020.68923] \textit{Melnikoff, Stephen J.; Quigley, Steven F.; Russell, Martin J.}, Speech recognition on an FPGA using discrete and continuous hidden Markov models, 202-211 [Zbl 1020.68807] \textit{Jamin, Antony; Mähönen, Petri}, FPGA implementation of the wavelet packet transform for high speed communications, 212-221 [Zbl 1020.68687] \textit{Carreira, A.; Fox, T. W.; Turner, L. E.}, A method for implementing bit-serial finite impulse response digital filters in FPGAs using JBits, 222-231 [Zbl 1020.68576] \textit{Manohararajah, Valavan; Borer, Terry; Brown, Stephen D.; Vranesic, Zvonko}, Automatic partitioning for improved placement and routing in complex programmable logic devices, 232-241 [Zbl 1020.68791] \textit{Kannan, Parivallal; Balachandran, Shankar; Bhatia, Dinesh}, Rapid and reliable routability estimation for FPGAs, 242-252 [Zbl 1020.68702] \textit{Danek, Martin; Muzikár, Zdenek}, Integrated iterative approach to FPGA placement, 253-262 [Zbl 1020.68601] \textit{Cabral, Lucídio A. F.; Aude, Júlio S.; Maculan, Nelson}, TDR: A distributed-memory parallel routing algorithm for FPGAs, 263-270 [Zbl 1020.68564] \textit{Kielbik, Rafal; Moreno, Juan Manuel; Napieralski, Andrzej; Jablonski, Grzegorz; Szymanski, Tomasz}, High-level partitioning of digital systems based on dynamically reconfigurable devices, 271-280 [Zbl 1020.68716] \textit{Yamaguchi, Yoshiki; Miyajima, Yosuke; Maruyama, Tsutomu; Konagaya, Akihiko}, High speed homology search using run-time reconfiguration, 281-291 [Zbl 1020.68955] \textit{Dyer, Matthias; Plessl, Christian; Platzner, Marco}, Partially reconfigurable cores for Xilinx Virtex, 292-301 [Zbl 1020.68618] \textit{Gericota, Manuel G.; Alves, Gustavo R.; Silva, Miguel L.; Ferreira, José M.}, On-line defragmentation for run-time partially reconfigurable FPGAs, 302-311 [Zbl 1020.68643] \textit{Poon, Kara K. W.; Yan, Andy; Wilton, Steven J. E.}, A flexible power model for FPGAs, 312-321 [Zbl 1020.68845] \textit{Cadenas, Oswaldo; Megson, Graham}, A clocking technique with power savings in Virtex-based pipelined designs, 322-331 [Zbl 1020.68565] \textit{Martina, Maurizio; Masera, Guido; Piccinini, Gianluca; Vacca, Fabrizio; Zamboni, Maurizio}, Energy evaluation on a reconfigurable, multimedia-oriented wireless sensor, 332-339 [Zbl 1020.68795] \textit{Todorovich, E.; Gilabert, M.; Sutter, G.; Lopez-Buedo, S.; Boemo, E.}, A tool for activity estimation in FPGAs, 340-349 [Zbl 1020.68917] \textit{Sutter, Gustavo; Todorovich, Elias; Lopez-Buedo, Sergio; Boemo, Eduardo}, FSM decomposition for low power in FPGA, 350-359 [Zbl 1020.68909] \textit{Nam, Gi-Joon; Sakallah, Karem; Rutenbar, Rob}, Hybrid routing for FPGAs by integrating Boolean satisfiability with geometric search, 360-369 [Zbl 1020.68824] \textit{Benkrid, K.; Crookes, D.; Benkrid, A.; Belkacemi, S.}, A Prolog-based hardware development environment, 370-380 [Zbl 1020.68544] \textit{Ho, C. H.; Leong, P. H. W.; Tsoi, K. H.; Ludewig, R.; Zipf, P.; Ortiz, A. G.; Glesner, M.}, Fly -- a modifiable hardware compiler, 381-390 [Zbl 1020.68670] \textit{Bolsens, Ivo}, Challenges and opportunities for FPGA platforms, 391-392 [Zbl 1020.68552] \textit{Kirimura, Masayuki; Takamoto, Yoshifumi; Mori, Takanori; Yasumoto, Keiichi; Nakata, Akio; Higashino, Teruo}, Design and implementation of FPGA circuits for high speed network monitors, 393-403 [Zbl 1020.68724] \textit{Gokhale, Maya; Dubois, Dave; Dubois, Andy; Boorman, Mike; Poole, Steve; Hogsett, Vic}, Granidt: Towards gigabit rate network intrusion detection technology, 404-413 [Zbl 1020.68646] \textit{Zhou, Kuan; Channakeshav; Guo, Jong-Ru; You, Chao; Goda, Bryan S.; Kraft, Russell P.; McDonald, John F.}, Fast SiGe HBT BiCMOS FPGAs with new architecture and power saving techniques, 414-423 [Zbl 1020.68972] \textit{Hall, Tyson S.; Hasler, Paul; Anderson, David V.}, Field-programmable analog arrays: A floating-gate approach, 424-433 [Zbl 1020.68654] \textit{Tanigawa, Kazuya; Hironaka, Tetsuo; Kojima, Akira; Yoshida, Noriyoshi}, A generalized execution model for programming on reconfigurable architectures and an architecture supporting the model, 434-443 [Zbl 1020.68911] \textit{Pionteck, T.; Zipf, P.; Kabulepa, L. D.; Glesner, M.}, A framework for teaching (re)configurable architectures in student projects, 444-451 [Zbl 1020.68843] \textit{Cho, Young H.; Navab, Shiva; Mangione-Smith, William H.}, Specialized hardware for deep network packet filtering, 452-461 [Zbl 1020.68591] \textit{Buerner, Thomas}, Implementation of a successive erasure BCH (16,7,6) decoder and performance simulation by rapid prototyping, 462-471 [Zbl 1020.68563] \textit{Ramírez, J.; García, A.; Meyer-Baese, U.; Lloris, A.}, Fast RNS FPL-based communications receiver design and implementation, 472-481 [Zbl 1020.68856] \textit{Haynes, Simon D.; Epsom, Henry G.; Cooper, Richard J.; McAlpine, Paul L.}, UltraSONIC: A reconfigurable architecture for video image processing, 482-491 [Zbl 1020.68660] \textit{Fox, Trevor W.; Turner, Laurence E.}, Implementing the discrete cosine transform using the Xilinx Virtex FPGA, 492-502 [Zbl 1020.68633] \textit{Staller, Alexander; Dillinger, Peter; Männer, Reinhard}, Implementation of the JPEG 2000 standard on a Virtex 1000 FPGA, 503-512 [Zbl 1020.68904] \textit{Beuchat, Jean-Luc; Tisserand, Arnaud}, Small multiplier-based multiplication and division operators for Virtex-II devices, 513-522 [Zbl 1020.68547] \textit{Gaffar, Altaf Abdul; Luk, Wayne; Cheung, Peter Y. K.; Shirazi, Nabeel; Hwang, James}, Automating customisation of floating-point designs, 523-533 [Zbl 1020.68639] \textit{Jang, Ju-wook; Choi, Seonil; Prasanna, Viktor K.}, Energy-efficient matrix multiplication on FPGAs, 534-544 [Zbl 1020.68689] \textit{Seng, Shay; Luk, Wayne; Cheung, Peter Y. K.}, Run-time adaptive flexible instruction processors, 545-555 [Zbl 1020.68885] \textit{de Sousa, José T.; Gonçalves, Fernando M.; Barreiro, Nuno; Moura, João}, DARP -- a digital audio reconfigurable processor, 556-566 [Zbl 1020.68605] \textit{Charlwood, Stephen; Mangnall, Jonathan; Quigley, Steven}, System-level modelling for performance estimation of reconfigurable coprocessors, 567-576 [Zbl 1020.68582] \textit{Ting, Kurt K.; Yuen, Steve C. L.; Lee, K. H.; Leong, Philip H. W.}, An FPGA based SHA-256 processor, 577-585 [Zbl 1020.68914] \textit{Zipf, P.; Glesner, M.; Bauer, C.; Wojtkowiak, H.}, Handling FPGA faults and configuration sequencing using a hardware extension, 586-595 [Zbl 1020.68974] \textit{Krasniewski, Andrzej}, On the set of target path delay faults in sequential subcircuits of lUT-based FPGAs, 596-606 [Zbl 1020.68744] \textit{Rebaudengo, M.; Reorda, M. Sonza; Violante, M.}, Simulation-based analysis of SEU effects on SRAM-based FPGAs, 607-615 [Zbl 1020.68858] \textit{Krasniewski, Andrzej}, Exploiting reconfigurability for effective testing of delay faults in sequential subcircuits of lUT-based FPGAs, 616-626 [Zbl 1020.68743] \textit{Matoušek, Rudolf; Tichý, Milan; Pohl, Zdeněk; Kadlec, Jiří; Softley, Chris; Coleman, Nick}, Logarithmic number system and floating-point arithmetics on FPGA, 627-636 [Zbl 1020.68798] \textit{Roesler, Eric; Nelson, Brent}, Novel optimizations for hardware floating-point units in a modern FPGA architecture, 637-646 [Zbl 1020.68864] \textit{Chiricescu, Silviu; Schuette, Michael; Glinton, Robin; Schmit, Herman}, Morphable multipliers, 647-656 [Zbl 1020.68589] \textit{Belanović, Pavle; Leeser, Miriam}, A library of parameterized floating-point modules and their use, 657-666 [Zbl 1020.68542] \textit{Stansfield, Tony}, Wordlength as an architectural parameter for reconfigurable computing devices, 667-676 [Zbl 1020.68905] \textit{Baleani, Massimo; Conti, Massimo; Ferrari, Alberto; Frascolla, Valerio; Sangiovanni-Vincentelli, Alberto}, An enhanced POLIS framework for fast exploration and implementation of I/O subsystems on CSoC platforms, 677-686 [Zbl 1020.68539] \textit{Wigley, Grant B.; Kearney, David A.; Warren, David}, Introducing ReConfigME: An operating system for reconfigurable computing, 687-697 [Zbl 1020.68943] \textit{Sidhu, Reetinder; Prasanna, Viktor K.}, Efficient metacomputation using self-reconfiguration, 698-709 [Zbl 1020.68891] \textit{Arias-Estrada, Miguel; Rodríguez-Palacios, Eduardo}, An FPGA co-processor for real-time visual tracking, 710-719 [Zbl 1020.68531] \textit{Fischer, Viktor; Drutarovský, Miloš; Lukac, Rastislav}, Implementation of 3-D adaptive LUM smoother in reconfigurable hardware, 720-729 [Zbl 1020.68630] \textit{Amira, A.; Bouridane, A.; Milligan, P.; Bensaali, F.}, Custom coprocessor based matrix algorithms for image and signal processing, 730-739 [Zbl 1020.68526] \textit{Aranki, Nazeeh; Moopenn, Alex; Tawel, Raoul}, Parallel FPGA implementation of the split and merge discrete wavelet transform, 740-749 [Zbl 1020.68530] \textit{Kerins, Tim; Popovici, Emanuel; Marnane, William; Fitzpatrick, Patrick}, Fully parameterizable elliptic curve cryptography processor over GF(2), 750-759 [Zbl 1020.68712] \textit{Hämäläinen, Antti; Tommiska, Matti; Skyttä, Jorma}, 6. 78 gigabits per second implementation of the IDEA cryptographic algorithm, 760-769 [Zbl 1020.68653] \textit{Moreira, Emmanuel A.; McAlpine, Paul L.; Haynes, Simon D.}, Rijndael cryptographic engine on the ultraSONIC reconfigurable platform, 770-779 [Zbl 1020.68822] \textit{Quisquater, Jean-Jacques; Standaert, Francois-Xavier; Rouvroy, Gael; David, Jean-Pierre; Legat, Jean-Didier}, A cryptanalytic time-memory tradeoff: First FPGA implementation, 780-789 [Zbl 1020.68853] \textit{Lauwereins, Rudy}, Creating a world of smart re-configurable devices, 790-794 [Zbl 1020.68756] \textit{Marescaux, Théodore; Bartic, Andrei; Verkest, Dideriek; Vernalde, Serge; Lauwereins, Rudy}, Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs, 795-805 [Zbl 1020.68793] \textit{Landaker, Wesley J.; Wirthlin, Michael J.; Hutchings, Brad L.}, Multitasking hardware on the SLAAC1-V reconfigurable computing system, 806-815 [Zbl 1020.68754] \textit{Valtonen, Tuomas; Isoaho, Jouni; Tenhunen, Hannu}, The case for fine-grained re-configurable architectures: An analysis of conceived performance, 816-825 [Zbl 1020.68926] \textit{Kokosinski, Zbigniew; Sikora, Wojciech}, An FPGA implementation of a multi-comparand multi-search associative processor, 826-835 [Zbl 1020.68735] \textit{Labbé, Anna; Pérez, Annie}, AES implementation on FPGA: Time-flexibility tradeoff, 836-844 [Zbl 1020.68750] \textit{Koeune, Francois; Rouvroy, Gael; Standaert, Francois-Xavier; Quisquater, Jean-Jacques; David, Jean-Pierre; Legat, Jean-Didier}, An FPGA implementation of the linear cryptanalysis, 845-852 [Zbl 1020.68734] \textit{Budiu, Mihai; Goldstein, Seth Copen}, Compiling application-specific hardware, 853-863 [Zbl 1020.68562] \textit{Cardoso, João M. P.; Weinhardt, Markus}, XPP-VC: A C compiler with temporal partitioning for the PACT-XPP architecture, 864-874 [Zbl 1020.68573] \textit{Tripp, Justin L.; Jackson, Preston A.; Hutchings, Brad L.}, Sea Cucumber: A synthesizing compiler for FPGAs, 875-885 [Zbl 1020.68920] \textit{Carletta, J. E.; Rayman, M. D.}, Practical considerations in the synthesis of high performance digital filters for implementation on FPGAs, 886-896 [Zbl 1020.68574] \textit{Meyer-Baese, U.; Ramírez, J.; García, A.}, Low power high speed algebraic integer frequency sampling filters using FPLDs, 897-904 [Zbl 1020.68810] \textit{Cardells-Tormo, Francisco; Valls-Coquillat, Javier}, High performance quadrature digital mixers for FPGAs, 905-914 [Zbl 1020.68572] \textit{Mencer, Oskar; Huang, Zhining; Huelsbergen, Lorenz}, HAGAR: Efficient multi-context graph processors, 915-924 [Zbl 1020.68808] \textit{Carrión Schäfer, Benjamin; Quigley, S. F.; Chan, A. H. C.}, Scalable implementation of the discrete element method on a reconfigurable computing platform, 925-934 [Zbl 1020.68577] \textit{Lam, Kai-Pui; Mak, Sui-Tung}, On computing transitive-closure equivalence sets using a hybrid GA-DP approach, 935-944 [Zbl 1020.68753] \textit{Salcic, Zoran; Roop, Partha; Biglari-Abhari, Morteza; Bigdeli, Abbas}, REFLIX: A processor core for reactive embedded applications, 945-954 [Zbl 1020.68873] \textit{Venkataramani, Girish; Sudhir, Suraj; Budiu, Mihai; Goldstein, Seth Copen}, Factors influencing the performance of a CPU-RFU hybrid architecture, 955-965 [Zbl 1020.68929] \textit{Sanz, A.; García-Nicolás, J. I.; Urriza, I.}, Implementing converters in FPLD, 966-975 [Zbl 1020.68876] \textit{Benitez, Domingo}, A quantitative understanding of the performance of reconfigurable coprocessors, 976-986 [Zbl 1020.68543] \textit{Buchenrieder, Klaus; Nageldinger, Ulrich; Pyttel, Andreas; Sedlmeier, Alexander}, Integration of reconfigurable hardware into system level design, 987-996 [Zbl 1020.68561] \textit{Wolz, Frank; Kolla, Reiner}, A retargetable macro generation method for the evaluation of repetitive configurable architectures, 997-1006 [Zbl 1020.68947] \textit{Ramaswamy, Ramaswamy; Tessier, Russell}, The integration of SystemC and hardware-assisted verification, 1007-1016 [Zbl 1020.68855] \textit{Kaviani, Alireza S.}, Using design hierarchy to improve quality of results in FPGAs, 1017-1026 [Zbl 1020.68709] \textit{Koutroumpezis, G.; Tatas, K.; Soudris, D.; Blionas, S.; Masselos, K.; Thanailakis, A.}, Architecture design of a reconfigurable multiplier for flexible coarse-grain implementations, 1027-1036 [Zbl 1020.68740] \textit{Kaneko, Naoto; Amano, Hideharu}, A general hardware design model for multicontext FPGAs, 1037-1047 [Zbl 1020.68701] \textit{Porrmann, Mario; Witkowski, Ulf; Kalte, Heiko; Rückert, Ulrich}, Dynamically reconfigurable hardware -- A new perspective for neural network implementations, 1048-1057 [Zbl 1020.68847] \textit{David, Raphael; Chillet, Daniel; Pillement, Sebastien; Sentieys, Olivier}, A compilation framework for a dynamically reconfigurable architecture, 1058-1067 [Zbl 1020.68604] \textit{Ichikawa, Shuichi; Yamamoto, Shoji}, Data dependent circuit for subgraph isomorphism problem, 1068-1071 [Zbl 1020.68683] \textit{Schmidt, Jan; Novotný, Martin; Jäger, Martin; Bečvář, Miloš; Jáchim, Michal}, Exploration of design space in ECDSA, 1072-1075 [Zbl 1020.68881] \textit{Damaj, Issam; Majzoub, Suhaib; Diab, Hassan}, 2D and 3D computer graphics algorithms under MORPHOSYS, 1076-1079 [Zbl 1020.68600] \textit{Blionas, S.; Masselos, K.; Dre, C.; Drosos, C.; Ieromnimon, F.; Pagonis, T.; Pneymatikakis, A.; Tatsaki, A.; Trimis, T.; Vontzalidis, A.; Metafas, D.}, A HIPERLAN/2 -- IEEE 802. 11a reconfigurable system-on-chip, 1080-1083 [Zbl 1020.68550] \textit{McBader, Stephanie; Clementel, Luca; Sartori, Alvise; Boni, Andrea; Lee, Peter}, SoftTOTEM: An FPGA implementation of the TOTEM parallel processor, 1084-1087 [Zbl 1020.68802] \textit{Yokota, Takashi; Nagafuchi, Masamichi; Mekada, Yoshito; Yoshinaga, Tsutomu; Ootsu, Kanemitsu; Baba, Takanobu}, Real-time medical diagnosis on a multiple FPGA-based system, 1088-1091 [Zbl 1020.68960] \textit{Aoyama, Kazuo; Sawada, Hiroshi}, Threshold element-based symmetric function generators and their functional extension, 1092-1096 [Zbl 1020.68529] \textit{Schlecker, Wolfgang; Engelhart, Achim; Teich, Werner G.; Pfleiderer, Hans-Jörg}, Hardware implementation of a multiuser detection scheme based on recurrent neural networks, 1097-1100 [Zbl 1020.68879] \textit{Hwang, James; Ballagh, Jonathan}, Building custom FIR filters using system generator, 1101-1104 [Zbl 1020.68682] \textit{Feske, Klaus; Heinrich, Georg; Fritzsche, Berndt; Langer, Mark}, SoC based low cost design of digital audio broadcasting transport network applications, 1105-1109 [Zbl 1020.68629] \textit{Jamro, Ernest; Wiatr, Kazimierz}, Dynamic constant coefficient convolvers implemented in FPGAs, 1110-1113 [Zbl 1020.68688] \textit{Kanus, Urs; Wetekam, Gregor; Hirche, Johannes; Meißner, Michael}, VIZARD II: An FPGA-based interactive volume rendering system, 1114-1117 [Zbl 1020.68703] \textit{Izu, Naoyuki; Yokoyama, Tomonori; Tsuchiya, Junichiro; Watanabe, Konosuke; Amano, Hideharu}, RHiNET/NI: A reconfigurable network interface for cluster computing, 1118-1121 [Zbl 1020.68685] \textit{Miletic, Filip; van Leuken, Rene; de Graaf, Alexander}, General purpose prototyping platform for data-processor research and development, 1122-1125 [Zbl 1020.68811] \textit{Kobori, Tomoyoshi; Maruyama, Tsutomu}, High speed computation of three dimensional cellular automata with FPGA, 1126-1130 [Zbl 1020.68732] \textit{Poussier, Sylvain; Rabah, Hassan; Weber, Serge}, SOPC-based embedded smart strain gage sensor, 1131-1134 [Zbl 1020.68849] \textit{Ha, Yajun; Hipik, Radovan; Vernalde, Serge; Verkest, Diederik; Engels, Marc; Lauwereins, Rudy; De Man, Hugo}, Adding hardware support to the HotSpot virtual machine for domain specific applications, 1135-1138 [Zbl 1020.68652] \textit{Gaudino, Roberto; De Feo, Vito; Chiaberge, M.; Sansoè, C.}, An FPGA-based node controller for a high capacity WDM optical packet network, 1139-1143 [Zbl 1020.68642] \textit{Calmon, F.; Fathallah, M.; Viverge, P. J.; Gontrand, C.; Carrabina, J.; Foussier, P.}, FPGA and mixed FPGA-DSP implementations of electrical drive algorithms, 1144-1147 [Zbl 1020.68567] \textit{Melis, Wim J. C.; Cheung, Peter Y. K.; Luk, Wayne}, Image registration of real-time broadcast video using the UltraSONIC reconfigurable computer, 1148-1151 [Zbl 1020.68804] \textit{Carline, Dylan; Coulton, Paul}, A novel watermarking technique for LUT based FPGA designs, 1152-1155 [Zbl 1020.68575] \textit{Henz, Martin; Tan, Edgar; Yap, Roland H. C.}, Implementing CSAT local search on FPGAs, 1156-1159 [Zbl 1020.68665] \textit{Niyonkuru, Adronis; Eggers, Göran; Zeidler, Hans Christoph}, A reconfigurable processor architecture, 1160-1163 [Zbl 1020.68831] \textit{Friebe, Sebastian; Köhler, Steffen; Spallek, Rainer G.; Juhr, Henrik; Künanz, Klaus}, A reconfigurable system-on-chip-based fast EDM process monitor, 1164-1167 [Zbl 1020.68635] \textit{Guccione, Steven A.; Keller, Eric}, Gene matching using JBits, 1168-1171 [Zbl 1020.68649] \textit{Saab, Daniel G.; Kocan, Fatih; Abraham, Jacob A.}, Massively parallel/reconfigurable emulation model for the \(d\)-algorithm, 1172-1176 [Zbl 1020.68871] \textit{Miyashita, Akira; Fujiwara, Toshihito; Maruyama, Tsutomu}, A placement/routing approach for FPGA accelerators, 1177-181 [Zbl 1020.68815]