Run-time-reconfigurable multi-precision floating-point matrix multiplier intellectual property core on FPGA (Q2399130)
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scientific article; zbMATH DE number 6763061
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| English | Run-time-reconfigurable multi-precision floating-point matrix multiplier intellectual property core on FPGA |
scientific article; zbMATH DE number 6763061 |
Statements
Run-time-reconfigurable multi-precision floating-point matrix multiplier intellectual property core on FPGA (English)
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21 August 2017
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FPGA
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run-time-reconfigurable
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variable-precision
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vedic mathematics
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Karatsuba
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0.731063723564148
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0.7214791774749756
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0.6974306106567383
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