Sequential fault modeling and test pattern generation for CMOS iterative logic arrays (Q3417048)

From MaRDI portal

!

This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:

scientific article; zbMATH DE number 5105687
Language Label Description Also known as
default for all languages
No label defined
    English
    Sequential fault modeling and test pattern generation for CMOS iterative logic arrays
    scientific article; zbMATH DE number 5105687

      Statements

      Identifiers