Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

DOI10.1109/12.888044MaRDI QIDQ3417048zbMATH OpenOpenAlexFDO

Authors Mihalis Psarakis, Dimitris Gizopoulos, Antonis Paschalis, Yervant Zorian

Publication date 9 January 2007

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/12.888044

zbMATH Keywords

iterative logic arrays

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Recommendations

• Testing CMOS combinational iterative logic arrays for realistic faults
• On the testability of iterative logic arrays
• Testing in two-dimensional iterative logic arrays
• Some remarks on the test complexity of iterative logic arrays (extended abstract)
• A testable design of iterative logic arrays

Cited in

(5)

• MODIFIED TRANSITION MATRIX AND FAULT TESTING IN SEQUENTIAL LOGIC CIRCUITS UNDER RANDOM STIMULI WITH A SPECIFIED MEASURE OF CONFIDENCE
• scientific article; zbMATH DE number 3672214 (Why is no real title available?)
• Testing CMOS combinational iterative logic arrays for realistic faults
• On the role of hardware reset in synchronous sequential circuit test generation
• Test generation for iterative logic arrays based on an N-cube of cell states model

This page was built for publication: Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3417048)