A testable design of iterative logic arrays

DOI10.1109/TCS.1981.1084934MaRDI QIDQ3912737zbMATH OpenOpenAlexFDO

Authors

Publication date 1981

Published in IEEE Transactions on Circuits and Systems (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tcs.1981.1084934

zbMATH Keywords

fault detectionfault diagnosisflow table augmentationtestability

Mathematics Subject Classification ID

Cellular automata (computational aspects) (68Q80) Fault detection; testing in circuits and networks (94C12)

Recommendations

• On the testability of iterative logic arrays
• Testing in two-dimensional iterative logic arrays
• Some remarks on the test complexity of iterative logic arrays (extended abstract)
• Testing CMOS combinational iterative logic arrays for realistic faults
• Testability Conditions for Bilateral Arrays of Combinational Cells

Cited in

(16)

• Testing in two-dimensional iterative logic arrays
• Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults
• On GID-testable two-dimensional iterative arrays
• IDDQ testing technology for one-dimensional iterative logic arrays
• On the testability of iterative logic arrays
• Built-In Testing of One-Dimensional Unilateral Iterative Arrays
• Sequential fault modeling and test pattern generation for CMOS iterative logic arrays
• Testability Conditions for Bilateral Arrays of Combinational Cells
• A design of programmable logic arrays with universal tests
• Design of easily testable combinational circuits
• Testing CMOS combinational iterative logic arrays for realistic faults
• Detection of multiple faults in two-dimensional ILAs
• Some remarks on the test complexity of iterative logic arrays (extended abstract)
• Test generation for iterative logic arrays based on an N-cube of cell states model
• Testable design of AND-EXOR logic networks with universal test sets
• Design of exclusive or sum-of-products (ESP) logic arrays with universal tests for detecting stuck-at and bridging faults

This page was built for publication: A testable design of iterative logic arrays

Report a bug (only for logged in users!)Click here to report a bug for this page (MaRDI item Q3912737)