Testing CMOS combinational iterative logic arrays for realistic faults

DOI10.1016/S0167-9260(96)00000-4MaRDI QIDQ4332045zbMATH OpenFDO

Authors Dimitris Gizopoulos, Dimitris Nikolos, Antonis Paschalis

Publication date 27 February 1997

Published in Integration (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1016/S0167-9260(96)00000-4

zbMATH Keywords

C-testabilityCell fault modelIterative logic arraysLinear-testabilitySequential faultsTest pattern generationVLSI testing

Mathematics Subject Classification ID

Computer system organization (68M99) Logic in artificial intelligence (68T27)

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• Testable design of two-dimensional cellular logic arrays for detecting struck-at and bridging faults
• Maximum ease of testability of logic circuits with respect to multiple stuck-on faults
• Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS
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• MODIFIED TRANSITION MATRIX AND FAULT TESTING IN SEQUENTIAL LOGIC CIRCUITS UNDER RANDOM STIMULI WITH A SPECIFIED MEASURE OF CONFIDENCE
• scientific article; zbMATH DE number 3672214 (Why is no real title available?)
• A testable design of iterative logic arrays
• Detection of multiple faults in two-dimensional ILAs
• Some remarks on the test complexity of iterative logic arrays (extended abstract)
• Testing and Diagnosing Comparison Faults of TCAMs with Asymmetric Cells
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