New Design for Testability Approach for Clock Fault Testing

DOI10.1109/TC.2011.59MaRDI QIDQ5277620zbMATH OpenFDO

Authors Cecilia Metra, Martin Omaña, T. M. Mak, S. Tam

Publication date 12 July 2017

Published in IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/TC.2011.59

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15) Fault detection; testing in circuits and networks (94C12)

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Cited in

(1)

• Localization of multiple faults with group control on a discrete device

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