A FPGA implementation of a phase locked loop for DC motor control (Q3574889)
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scientific article; zbMATH DE number 5730168
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
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| English | A FPGA implementation of a phase locked loop for DC motor control |
scientific article; zbMATH DE number 5730168 |
Statements
2 July 2010
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PLL
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ADPLL
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FPGA
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motor control
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0.7083598375320435
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0.7074759602546692
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0.6973142623901367
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