VLSI Architectures for Computing Multiplications and Inverses in GF(2<sup>m</sup>) (Q3682399)

From MaRDI portal

!

This is the item page for this Wikibase entity, intended for internal use and editing purposes. Please use the normal view instead:

scientific article; zbMATH DE number 3904498
Language Label Description Also known as
default for all languages
No label defined
    English
    VLSI Architectures for Computing Multiplications and Inverses in GF(2<sup>m</sup>)
    scientific article; zbMATH DE number 3904498

      Statements

      VLSI Architectures for Computing Multiplications and Inverses in GF(2<sup>m</sup>) (English)
      0 references
      0 references
      0 references
      0 references
      0 references
      0 references
      0 references
      1985
      0 references
      systolic array
      0 references
      Finite field arithmetic logic
      0 references
      VLSI
      0 references
      pipeline structure
      0 references
      Massey-Omura multiplier
      0 references

      Identifiers

      0 references
      0 references
      0 references
      0 references
      0 references
      0 references