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scientific article; zbMATH DE number 177240
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| default for all languages | No label defined |
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| English | No label defined |
scientific article; zbMATH DE number 177240 |
Statements
18 May 1993
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verification of sequential machines
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behavioral equivalence
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temporal logic
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verification algorithm
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Boolean function
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typed decision graphs
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0.8398566842079163
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