Funktioneller Test der Auflösung von Zugriffskonflikten in Mehrrechnersystemen. (Functional testing of access arbitration in multiprocessor systems) (Q4040340)

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scientific article; zbMATH DE number 193538
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    Funktioneller Test der Auflösung von Zugriffskonflikten in Mehrrechnersystemen. (Functional testing of access arbitration in multiprocessor systems)
    scientific article; zbMATH DE number 193538

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      5 June 1993
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      multiprocessor
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      collision resolution
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      dissertation
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      functional testing
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      access arbitration
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      fault tolerant multiple processor environment
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      bus arbitration
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      Funktioneller Test der Auflösung von Zugriffskonflikten in Mehrrechnersystemen. (Functional testing of access arbitration in multiprocessor systems) (English)
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      In volume 175 of the ``Informatik-Fachberichte'' the author presents his dissertation thesis delivered at the Institute of Computer Design and Fault Tolerance of the University Karlsruhe. The subject of the dissertation is functional testing of access arbitration to global resources in fault tolerant multiple processor environment - especially functional testing of bus arbitration. After a short overview of general system test strategies follow a model for access arbitration to common resources, a description of the fundamentals of the proposed test procedure and a classification of access conflicts and arbitration faults. The actual proposed test procedure consists of - the access synchronization phase, in which the access of all competing units is brought into a defined order, - the access conflict phase, in which the defined access conflicts are produced and tested. All processors participating in the test run program loops of a carefully calculated length of time. Exchange of control information between the processors (for varying the length of the program loops) is realized via a common memory which is necessary for the test. The test needs no additional hardware. The length of the program loops depends on the number of processors taking part in the test, the test phase and the position of the processor in the access sequence. During the test no other access is possible to the common resource.
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