No label defined (Q4948148)

The emphasis of this textbook is on the question how to develop Verilog RTL models which support the verification processes of complex designs. It starts with a description of various components of the verification process such as test strategies, coverage analysis, event monitoring and assertion checking. This description is followed by two chapters dedicated to the definition and motivation of a Verilog RTL verifiable subset and its relation to simulation performance. A further chapter gives a brief introduction to formal verification where the emphasis is mostly on how to support formal verification by certain coding styles rather than on the formal verification process itself. The book concludes with a chapter that presents a verifiable RTL coding style, a chapter that explains the possible problems wich will arise if designers don't follow a verifiable RTL coding style, the so called bad stuff, and finally a verifiable RTL tutorial and a collection of principles that have been found and motivated throughout the book. The book is characterized by the experience of the authors in large scale design projects. It contains a lot of ideas for experienced Verilog designers to set up coding styles for large design projects in order to support and simplify verification and to work around the deficencies of the Verilog language and state of the art EDA tools.