An efficient DC-gain matched balanced truncation realization for VLSI interconnect circuit order reduction (Q6824562)
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scientific article
| Language | Label | Description | Also known as |
|---|---|---|---|
| default for all languages | No label defined |
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| English | An efficient DC-gain matched balanced truncation realization for VLSI interconnect circuit order reduction |
scientific article |
Statements
60
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1-2
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3-15
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January 2002
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Xuan Zeng
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Dian Zhou
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Wei Cai
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