Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture

DOI10.1109/TSP.2012.2197749MaRDI QIDQ4573953zbMATH OpenOpenAlexFDO

Authors Yeong-Luh Ueng, Yu-Luen Wang, Li-Sheng Kan, Chung-Jay Yang, Yung-Hsiang Su

Publication date 18 July 2018

Published in IEEE Transactions on Signal Processing (Search for Journal in Brave)

Full work available at URL https://doi.org/10.1109/tsp.2012.2197749

Mathematics Subject Classification ID

Convolutional codes (94B10) Decoding (94B35)

Cited in

(2)

• A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes
• Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

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